1. Field of the Invention
The present invention relates to an input/output (I/O) circuit for a programmable logic circuit (e.g., a field programmable gate array or a complex programmable logic device, known to those skilled in the art). In particular, the present invention relates to an I/O circuit with bidirectional input and output, and shift register capabilities.
2. Description of the Related Art
In a programmable logic circuit, the I/O pins of the integrated circuit are each associated with an I/O circuit or cell, which is used to either receive an input signal from the associated pin, or to drive an output signal onto the associated pin. One example of an I/O cell in the prior art is described in U.S. Pat. No. 6,034,541, entitled xe2x80x9cIn-system Programmable Interconnect Circuitxe2x80x9d to Kopec et al., filed on Apr. 7, 1997, issued on Mar. 7, 2000, which is assigned to Lattice Semiconductor Corporation, also the Assignee of the present application. The disclosure of U.S. Pat. No. 6,034,541 is hereby incorporated by reference in its entirety to provide background information.
Typically an I/O cell provides only a single flip-flop which is configurable to either latch the input signal, or to provide a registered output signal. In order to provide bidirectional operations using the I/O circuit, a 1-bit output register is configured from the general-purpose configurable logic circuits in the programmable logic circuit. Not only is this arrangement cumbersome, providing an output register in this manner results in a circuit that does not meet performance requirements typical of many telecommunication or data communication applications.
An input/output (I/O) circuit or cell associated with a pin of a programmable logic circuit allows the pin to be configured as for bidirectional input and output operations, without requiring a second one-bit register to be configured from the configurable logic elements of the programmable logic circuit. The I/O cell can be used in parallel-to-serial, serial-to-parallel and shift register operations.
In one embodiment of the present invention, the input/output (I/O) circuit includes input and output flip-flops for capturing an input signal and for providing an output signal, respectively, and multiplexers for routing signals between the input and output flip-flops. Additional multiplexers and routing resources can be provided to route the input signal, the output signal and other signals to other portions of the programmable logic circuit and other I/O circuits. In one implementation, the routing resource provides additional input signals, global clocks and other control signals.
By suitably configuring the input flip-flop, the output flip-flop and various multiplexers, the present invention allows a group of I/O circuits to provide serial-to-parallel, parallel-to-serial and shift register operations.
In one embodiment, a control flip-flop is provided in the I/O circuit to provide a registered control signal (e.g., an output enable signal).
By providing input, output and bidirectional operations without calling on configurable logic elements in the programmable logic circuit, the I/O circuits of the present invention meet high performance requirements of telecommunication and data communication applications.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.